1. Field of the Invention
The present invention relates to a field-effect transistor, and especially relates to a field-effect transistor using gallium arsenide as material.
2. Description of Related Art
As a microfabrication technique advances, a semiconductor device that includes a field-effect transistor using gallium arsenide as, material (hereinafter, to be sometimes referred to as a GaAs device) is supplied in a low price. The GaAs device is widely used as a Switch IC (SWIC) for small-sized, high-frequency operated electronics, such as a mobile phone and a PDA.
For the mobile handset, a SWIC with low harmonic distortion characteristics is in great demand. A general SWIC includes a DC-DC boost converter fabricated by Si CMOS process and a GaAs FET package. Biased at a high control voltage boosted by the DC-DC converter, the device exhibits high isolation characteristics and low harmonic distortion characteristics. A technique related to the GaAs device having such configuration is known in the following conventional examples 1 to 3.
The conventional example 1 (Japanese Patent Application Publication (JP 2004-193273A)) discloses a heterojunction type compound semiconductor field-effect transistor having a gate electrode in a recess portion formed by a selective etching utilizing an undoped InGaP stopper layer. FIG. 1 is a cross-sectional view showing a structure of the heterojunction type compound semiconductor field-effect transistor described in the conventional example 1. As shown in FIG. 1, in the conventional heterojunction type compound semiconductor field-effect transistor, a semi-insulating GaAs substrate 111, a buffer layer 112, an n-AlGaAs electron supply lower layer 113, an i-InGaAs channel layer 114, an n-AlGaAs electron supply layer 115, an i-InGaP electric field moderating layer 116, an n-GaAs contact lower layer 117, a recess stopper layer 150, and an n+-GaAs contact upper layer 118 are laminated in order.
An undoped GaAs layer formed as the buffer layer 112 on the semi-insulating GaAs substrate 111. An n-Al0.2Ga0.8As layer is laminated as the n-AlGaAs electron supply lower layer 113 on the buffer layer 112. An i-Al0.2Ga0.8As layer is formed as a lower-side spacer layer (not shown) on the n-AlGaAs electron supply lower layer 113. An i-In0.15Ga0.85As layer is formed as the i-InGaAs channel layer 114 on the lower-side spacer layer. An i-Al0.2Ga0.8As layer is laminated as an upper-side spacer layer (not shown) on the i-InGaAs channel layer 114, and an n-Al0.2Ga0.8As layer is laminated as the upper-side n-AlGaAs electron supply layer 115 on the i-InGaAs channel layer 114. An i-In0.48Ga0.52P layer is formed as the i-InGaP electric field moderating layer 116 on the n-AlGaAs electron supply layer 115. In addition, an n-GaAs layer is formed as the n-GaAs contact lower layer 117 (a first contact layer). Moreover, a low-resistance n+-GaAs layer is formed as the n+-GaAs contact upper layer 118 (a second contact layer). The respective layers are laminated in order. An i-In0.49Ga0.51P layer is laminated as the recess stopper layer 150 on the n-GaAs contact lower layer 117. A low-resistance n+-GaAs layer is laminated as the n+-GaAs contact upper layer 118 on the recess stopper layer 150. A source electrode 120 and a drain electrode 121, each of which includes Ni—AuGe—Au alloy layer, are formed on a surface of the n+-GaAs contact upper layer 118, so that a wide recess opening 105 can be put between the electrodes. In the n+-GaAs contact upper layer 118, the wide recess opening 105 is formed by an etching of the n+-GaAs contact upper layer 118. Inside the wide recess opening 105, a narrow recess opening 110 having a narrower width than an opening width of the wide recess opening 105 is formed by an etching of the recess stopper layer 150, the n-GaAs contact lower layer 117, and the i-InGaP electric field moderating layer 116. A gate electrode 122 including Al is formed on a surface of the n-AlGaAs electron supply layer 115 exposed to a bottom portion of the narrow recess opening 110.
FIG. 2 is a cross-sectional view showing another structure of the heterojunction type compound semiconductor field-effect transistor described in conventional example 1. As shown in FIG. 2, the recess stopper 150 is not provided in the heterojunction type compound semiconductor field-effect transistor. The wide recess opening 105 is formed by an etching of the n+-GaAs contact upper layer 118. The narrow recess opening 110 is formed inside the wide recess opening 105 by an etching of the n-GaAs contact lower layer 117 and the i-InGaP electric field moderating layer 116 and to have a narrower width than the opening width of the wide recess opening 105. The heterojunction type compound semiconductor field-effect transistor has a double-recess structure of the wide recess opening 105 and the narrow recess opening 110.
A gate electrode 122 including, for example, Al is formed on a surface of the n-AlGaAs electron supply layer 115 exposed to a bottom portion of the narrow recess opening 110. The source electrode 120 and the drain electrode 121, each of which includes, for example, a Ni—AuGe—Au alloy layer, are formed on the above-described n+-GaAs contact upper layer 118, so that the above-mentioned wide recess opening 105 can be put between the electrodes. The n-GaAs contact lower layer 117 defining the narrow recess opening 110 contains GaAs to which an n-type impurity is added, and the n+-GaAs contact upper layer 118 defining the wide recess opening 105 is also formed by containing GaAs to which the n-type impurity is added in higher concentration. Furthermore, the i-InGaP electric field moderating layer 116 is formed of intrinsic-type InGaP.
In addition, the conventional example 2 (Japanese Patent Application Publication (JP-A-Heisei 7-335867A)) discloses a technique related to a heterojunction type compound semiconductor field-effect transistor of a double-recess structure to which a selective etching technique can be applied, and which has a high performance, and has good uniformity and good reproductivity. Moreover, the conventional example 3 (Japanese Patent Application Publication (JP 2002-526922A)) discloses a technique related to a pseudomorphic high electron mobility transistor.
Since a potential barrier to electrons from an ohmic electrode to a channel layer is formed in the double-recess structure in which the InGaP layer and the AlGaAs layer are inserted into a GaAs cap layer, a contact resistance will become high. In addition, since a layer having low impurity concentration is employed as an electric field moderating layer in the GaAs cap layer, a potential barrier of the InGaP layer rises. Therefore, the contact resistance will become high. Thus, in a conventional FET structure that a gate electrode is arranged in a gate recess section formed with an InGaP stopper layer, it was difficult to realize a low gate leakage current and a low on-resistance at a same time.
In addition, when the cap layer consists of only a highly Si impurity doped semiconductor layer, the device will exhibit a low drain breakdown voltage.